Peking University Team Develops Millisecond Neuromorphic Dynamics Chip Based on Phase-Change Memristors, Accelerating Cortex Reconstruction by Nearly 480x

On July 2, 2025, a team led by Yang Yuchao from Peking University, in collaboration with Song Zhitang's group from the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, published a paper in Science reporting the world's first millisecond neuromorphic dynamics system chip based on phase-change memory (PCM) memristors. Fabricated in 40nm technology, the chip leverages the controllable conductance drift of PCM devices for in-situ step-size search and integrates compute-in-memory to accelerate neural network inference, reducing the single iteration latency of neuromorphic dynamics to 2.12 milliseconds. In brain cortex surface reconstruction tasks, it achieves 50.38x to 478.18x speedup and 11.75x to 24.73x power reduction compared to an NVIDIA A100 GPU.

Background and Challenges

Neuromorphic dynamics systems (NDS) embed neural networks into differential equation solvers, offering higher accuracy than traditional methods in high-fidelity geometric modeling (e.g., cortex reconstruction), but suffer from slow computation. Traditional digital hardware (GPUs, ASICs) is limited by the memory wall and frequent data movement, with single iterations taking hundreds of milliseconds. Key bottlenecks include high-cost adaptive step-size search, large latency in embedded neural network (ENN) inference, and lack of dedicated support for special computation kernels (e.g., square root).

Core Innovations

• Controllable Conductance Drift (CCD): The team discovered that the conductance of PCM devices drifts predictably and controllably over time, and used this to encode the step size Δt, turning step-size search into a physical evolution process, eliminating read/write and multiplication operations in traditional digital circuits.
• Compute-in-Memory (CIM): Utilizing the multi-level conductance of PCM, ENN weights are programmed into memristor arrays, and multiply-accumulate operations are performed in the analog domain in situ, avoiding data movement. A dual-column differential structure supports 16 conductance states (8 levels), covering weight matrices from 32×32 to 128×128.

Chip Architecture and Performance

The chip is fabricated in 40nm technology, runs at 50 MHz, and contains a 288×512 PCM 1T1R array (approximately 147,000 devices). The combined area of compute-in-memory and step-size drift arrays is only 0.28 mm². A single NDS iteration (fourth-order Runge-Kutta) consists of four steps: ENN compute-in-memory, conductance drift step-size search, intermediate quantity combination, and output with error estimation. Compared to a dedicated ASIC, it achieves 3.82x to 36.27x speedup and 11.75x to 24.73x power reduction.

Application Validation: Cortex Reconstruction

The team applied the chip to reconstruct white matter and gray matter cortical surfaces, generating non-self-intersecting closed manifold meshes. It meets high-fidelity requirements in terms of average symmetric surface distance (ASSD) and Hausdorff distance (HD). Compared to FreeSurfer (8722–11860 seconds) and GPU A100 (1.83–21.47 seconds), the PCM-NDS chip reduces processing time to 3.85 ms to 426.31 ms, achieving a maximum speedup of 478.18x.

Impact and Evaluation

This work pushes real-time computation of neuromorphic dynamics systems to the millisecond level for the first time, providing a hardware foundation for brain-computer interfaces, brain digital twins, and neuronavigation. Science published a concurrent commentary, calling it "a paradigm shift toward physics-driven computing."