Huawei Updates Tao Scaling Paper: Adds Mass Production Data and Engineering Details, Proposes New Post-Moore Time Scaling Paradigm

He Tingbo, head of Huawei's semiconductor business, updated the τ scaling (Tao Scaling) paper (ChinaXiv:202605.00224v2) on July 3, 2026, significantly supplementing engineering details, mass production measurement data, and product plans based on the original theoretical framework. The paper proposes using a unified characteristic time constant τ as a full-stack optimization target, replacing traditional Moore's geometric scaling, covering 12 orders of magnitude in time from transistors (picoseconds) to data centers (seconds).

Key Updates and Measured Data

• Mobile SoC Scenario: Using LogicFolding technology, digital, analog, and memory circuits are vertically stacked via wafer-to-wafer hybrid bonding. At the same process node, the next-generation Kirin chip achieves a transistor density increase from 155 to 238 million transistors per square millimeter (a 55% increase), a 41% reduction in power consumption at equivalent performance, and a 13% increase in maximum frequency compared to the previous planar chip.
• AI Computing System Scenario: Proposes the Unified Bus interconnect protocol (reducing cross-node latency from tens of microseconds to approximately 100 nanoseconds), the Hi-ONE high-density optical interconnect engine (8 Tb/s bandwidth per module, using analog equalization drivers instead of high-power DSPs), and 3D Folding (moving memory, power supply, and optical modules to the chip surface to address the bottleneck where computing power grows as N² while bandwidth only grows linearly). It is expected to increase hardware integration by more than 100 times by 2035.

Technology Selection and Engineering Challenges

• Abandoning Sequential 3D Integration: Due to yield issues (high-temperature processes causing performance degradation in bottom-layer transistors), the more mature wafer-to-wafer hybrid bonding route was chosen.
• Heat Dissipation Issue First Disclosed: Thermal-aware partitioning and layout are used to stagger high-power modules in three-dimensional space, but this only mitigates the problem and does not fundamentally solve it.
• Pitch Ratio (ratio of bonding layer pitch to top metal wiring pitch): This is a key parameter for LogicFolding; sufficiently dense bonding pitch enables a transition from discrete optimization to continuous optimization.

Industry Significance

τ scaling theory provides a standardized post-Moore development framework for manufacturers unable to keep up with cutting-edge lithography, elevating advanced packaging, on-chip interconnects, and optical interconnects to core competencies. Based on engineering practices from 381 chips delivered in mass production from May 2020 to May 2026, the paper has evolved from a theoretical hypothesis into a complete system with mass production evidence and a clear industrial roadmap.